Application module: Interconnect placement requirements ISO/TS 10303-1690:2018-11(E)
© ISO

Cover page
Table of contents
Copyright
Foreword
Introduction
1 Scope
2 Normative references
3 Terms, definitions and abbreviated terms
    3.1 Terms and definitions
    3.2 Abbreviated terms

4 Information requirements
   4.1 Required AM ARM
   4.2 ARM type definitions
   4.3 ARM entity definitions
   4.4 ARM subtype constraint definitions
   4.5 ARM function definitions
5 Module interpreted model
   5.1 Mapping specification
   5.2 MIM EXPRESS short listing
     5.2.1 MIM type definitions
     5.2.2 MIM entity definitions
     5.2.3 MIM subtype constraint definitions

A MIM short names
B Information object registration
C ARM EXPRESS-G   EXPRESS-G
D MIM EXPRESS-G   EXPRESS-G
E Computer interpretable listings
F Change history
Bibliography
Index

Mapping tableIndex of EXPRESS-G pagesFirst pagePrevious pageNext pageLast page
Figure C.2 — ARM entity level EXPRESS-G diagram 1 of 2 ../interconnect_placement_requirements/sys/4_info_reqs.htm#interconnect_placement_requirements_arm.interconnect_module_design_object_category_or_group ../interconnect_placement_requirements/sys/4_info_reqs.htm#interconnect_placement_requirements_arm.interconnect_module_design_object_select ../interconnect_placement_requirements/sys/4_info_reqs.htm#interconnect_placement_requirements_arm.ipr_requirement_assignment_item ./armexpg3.htm ../non_feature_shape_element/sys/4_info_reqs.htm#non_feature_shape_element_arm.non_feature_shape_element_relationship ../non_feature_shape_element/sys/4_info_reqs.htm#non_feature_shape_element_arm.non_feature_shape_element ../layered_interconnect_module_design/sys/4_info_reqs.htm#layered_interconnect_module_design_arm.component_termination_passage ../layered_interconnect_module_design/sys/4_info_reqs.htm#layered_interconnect_module_design_arm.layered_interconnect_module_design_view ../layered_interconnect_module_design/sys/4_info_reqs.htm#layered_interconnect_module_design_arm.inter_stratum_feature ../layered_interconnect_module_design/sys/4_info_reqs.htm#layered_interconnect_module_design_arm.inter_stratum_extent ../layered_interconnect_module_design/sys/4_info_reqs.htm#layered_interconnect_module_design_arm.cutout ../layered_interconnect_module_design/sys/4_info_reqs.htm#layered_interconnect_module_design_arm.conductive_filled_area ../layered_interconnect_module_design/sys/4_info_reqs.htm#layered_interconnect_module_design_arm.conductor ../requirement_assignment/sys/4_info_reqs.htm#requirement_assignment_arm.requirement_assignment ../non_feature_shape_element/sys/4_info_reqs.htm#non_feature_shape_element_arm.non_feature_shape_element_relationship ../layered_interconnect_module_design/sys/4_info_reqs.htm#layered_interconnect_module_design_arm.stratum_feature ../layered_interconnect_module_design/sys/4_info_reqs.htm#layered_interconnect_module_design_arm.via ../land/sys/4_info_reqs.htm#land_arm.land ../requirement_assignment/sys/4_info_reqs.htm#requirement_assignment_arm.requirement_assignment ../layered_interconnect_module_design/sys/4_info_reqs.htm#layered_interconnect_module_design_arm.layered_interconnect_module_design_view ../requirement_assignment/sys/4_info_reqs.htm#requirement_assignment_arm.requirement_assignment_item ../group/sys/4_info_reqs.htm#group_arm.group ../layered_interconnect_module_design/sys/4_info_reqs.htm#layered_interconnect_module_design_arm.stratum ../layered_interconnect_module_design/sys/4_info_reqs.htm#layered_interconnect_module_design_arm.stratum ../layered_interconnect_module_design/sys/4_info_reqs.htm#layered_interconnect_module_design_arm.laminate_component ../layered_interconnect_module_with_printed_component_design/sys/4_info_reqs.htm#layered_interconnect_module_with_printed_component_design_arm.printed_component ../layered_interconnect_module_design/sys/4_info_reqs.htm#layered_interconnect_module_design_arm.stratum ../interconnect_placement_requirements/sys/4_info_reqs.htm#interconnect_placement_requirements_arm.interconnect_module_design_object_category ../interconnect_placement_requirements/sys/4_info_reqs.htm#interconnect_placement_requirements_arm.interconnect_module_constraint_region ../interconnect_placement_requirements/sys/4_info_reqs.htm#interconnect_placement_requirements_arm.stratum_constraint_region ../interconnect_placement_requirements/sys/4_info_reqs.htm#interconnect_placement_requirements_arm.ipr_non_feature_shape_element_subtypes


Figure C.2 — ARM entity level EXPRESS-G diagram 1 of 2


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